1. Field of the Invention
The present invention concerns an input/output controller intended to interact with a central processor unit of a computer which communicates with various peripheral electronic equipment. This input/output controller may be used in particular in the field of avionics.
2. Discussion of the Background
Currently, there are a plurality of computers present at the same time in aircraft, each driving a single application. The term application is intended for example to mean the automatic pilot, the ground proximity detection system, the system for protection against stalling, etc.
In each computer, the central processor unit is connected by a parallel bus to the peripheral electronic equipment belonging to the application in question. This link by a parallel bus makes it possible to transmit information at a high rate, but requires a large number of connection pins.
Such a link involves a certain degree of insecurity because, if a fault occurs, all the data carried on this link are lost. Since each application is processed independently of the others, this insecurity is tolerable.
With the significant progress in the speed and capacity of the processors, and with a view to reducing costs, it is conceivable for only a single central processor unit to drive a plurality of applications. In order not to compromise the security involved with processing a plurality of applications in the same central processor unit, the invention relates to an input/output controller which interfaces between the central processor unit of a computer and the various peripheral electronic equipment belonging to these applications.
The present invention provides an input/output controller intended to interact with a central processor unit of a computer which communicates with peripheral electronic equipment, and connected on the one hand to the central processor unit and on the other hand to the peripheral electronic equipment, characterized in that the link with the central processor unit is produced with an input serial line and at least one output serial line, and in that it receives instructions of a first type from the central processor unit via the input serial line and instructions of at least one second type which are stored in a memory external to the central processor unit which it processes using a sequencer device which allocates time slots to the instructions according to their type.
This input/output controller is self-contained and can operate with all types of central processor unit and peripheral electronic equipment.
One or more types of instructions from the memory may be described as pseudo-instructions formed by lists of analogue values which are stored in the memory, the various types corresponding to lists of values of different natures.
Certain instructions other than pseudo-instructions from the memory may form sequences which are executed after reception of a synchronization instruction.
The sequencer device may allocate equal time slots for the successive processing of each of the types of instructions, then allows itself an optionally zero time interval without processing before recommencing the processing. Each type of instructions is processed with the same frequency.
More sophisticated sequencing may be envisaged so as to allow processing with frequencies matched to the various types of instructions. Such sequencing gives a much better solution to the needs encountered in an avionics application.
The sequencer device may allocate equal time slots to the processing of the instructions according to their type, each type of instructions being assigned an occurrence period, the first type of instructions which is processed having the shortest period, this period being referred to as the reference period, and a phase referred to as the reference phase, the other types of instructions having a phase constraint in relation to the reference phase, these other types of instructions being processed with a rank which is a function of the increasing order of their phase constraint, their period being a multiple of the reference period.
It is simpler to choose by convention a zero reference phase.
The reference period may be a multiple of a duration, referred to as the base period, which corresponds to the access time for an instruction in the memory.
It is advantageous to express the phase constraint of the second type of instructions which is processed by a phase increment in relation to the reference phase. The phase constraint of the types of instructions of rank higher than 2 is expressed by a phase increment in relation to the phase constraint of the type of instructions which is processed in the preceding rank.
A sequencer device for processing the various types of instructions with different frequencies may have:
a device delivering a phase referred to as the current phase from a base clock whose period corresponds to the access time for an instruction in the memory,
a first divider of the base clock which receives, in addition to the base clock, the value of the reference period and which generates pulses having the reference period and the reference phase;
one predivider and divider assembly associated respectively with each of the other types of instructions to be processed, and receiving the base clock and the reference period,
each predivider receiving the value of the reference period and a start signal originating from the comparison between the phase constraint of the associated type of instructions and the current phase, and generating, in the direction of the divider of the same assembly as itself, a signal which has a period equal to the reference period and is phased according to the phase constraint of the associated type of instructions,
each divider generating pulses having the period and the phase constraint of the associated type of instructions.
The device delivering the current phase may be produced by a saturation counter receiving the base clock.
The saturation counter may be zeroed when the input/output controller is reengaged or by a signal delivered by a reset device.
Each predivider may be associated with a comparator which delivers the start signal to it, each comparator receiving the current phase and the phase constraint, in relation to the reference phase, of the associated type of instructions.
The first comparator directly receives the value of the phase increment of the second type of instructions in relation to the reference phase, whereas the other comparators are each associated with an adder, each adder delivering the phase constraint, in relation to the reference phase, of the associated type of instructions, and receiving the phase constraint of the type of instructions which is processed with the preceding rank and the value of the phase increment in relation to the said constraint.
An instruction other than a pseudo-instruction may be of the ARINC 429 type and have thirty-two bits, including a code on at most eight bits and a parameter on at most twenty-one bits.
The values of the occurrence periods and of the phase constraints of the various types of instructions may be coded in the parameter of one or more loading instructions.
The input/output controller according to the invention may have a code analysis device which decodes the codes of the instructions.
A pseudo-instruction is executed under the control of an activation instruction. It has, on thirty-two bits, a list of analogue values which are coded either in the form of increments or in the form of absolute values.
The input/output controller may, for managing the pseudo-instructions, have drive means for the pseudo-instructions which receive the activation instructions, which keep the codes of the activation instructions and deal with access to the memory via an access pointer. The code analysis device receives the pseudo-instructions and the codes of the activation instructions from the drive means for the pseudo-instructions.
If a plurality of accesses to the memory are necessary in order to extract an instruction, it is desirable for the input/output controller to have management means for the memory with a buffer unit driven by the sequencer device. The buffer unit may also be driven by the drive means for the pseudo-instructions.
The management means for the memory may also have a sequencer device for downloading to the memory on the basis of instructions received from the central processor unit.
It is advantageous for the input/output controller to be able to communicate in acquisition mode or in generation mode with the peripheral electronic equipment by a plurality of two-way interface channels which can be configured in particular as a parallel bus, as a link carrying Boolean operations, as a serial link and as a link with an optical coder, and to that end the input/output controller may have at least one interface device connected to the peripheral electronic equipment by at least one of the these interface channels. This interface device is entirely standard.
In the same way, an interface device may be provided for interfacing with the central processor unit, connected to the central processor unit by the input and output lines.